The invention relates to an electronic arrangement and method for utilising synchronous RAM modules with an asynchronous memory controller. More particularly, the invention is directed towards a converter and related method to convert asynchronous RAM control signals to synchronous RAM control signals.
Random access memory (RAM) devices provide electronic storage of data in cells. Each cell is referenced by a memory address. To reduce die costs, RAM is typically arranged as a table of cells wherein, typically, each cell contains one bit of binary data, although memory configurations are available wherein multiple bits are associated with each address. Addresses are split into halves, with each half identifying a row and column of the table of cells. Table cells are accessed selectively by activating appropriate rows and columns of the RAM devices. The intersecting cell of the row and column contains the data associated with the full address.
Inputs to RAM include plurality of address lines, a data line (which is also an output line) and a plurality of control lines determining whether data is being written or read at a location indicated by the addresses present at the address lines. Generally the control signals are provided to the RAM by memory control system which may be embodied in a logic circuit, a dedicated memory controller device or a microprocessor.
To specify a read, write or refresh operation, the Row Access Strobe (RAS), the Column Access Strobe (CAS) and the Write Enable (WE) control lines are selectively activated for the RAM. The timing of the assertion and deassertion of the RAS, CAS and WE control lines determine whether a read, write or refresh operation is being specified.
When a RAS control signal is activated, the upper half of the address present on the address lines is decoded and used to activate a corresponding row of table cells in the RAM. To complete a cell access, the CAS control line is activated and the lower half of the full address is used to activate a corresponding column of tables of cells.
Synchronization for read, write or refresh operations for RAM may be done synchronously, based on a clock pulse, and asynchronously, based on elapsed time. Memory devices have been developed to-conform to operating timing parameters for each synchronization method.
In asynchronous operation, a specific amount of time must elapse to ensure that a read or a write operation for the RAM is complete. Several asynchronous timing protocols for RAM have been developed which are known in the art. In particular, Extended Data Out (EDO) asynchronous RAM has been a commercially accepted format. EDO RAM utilizes output buffers of the memory which are not deactivated on the rising edge of the CAS. Essentially, the column precharge time is eliminated when data is latched out. Another asynchronous memory protocol is Fast Page Mode.
Synchronous dynamic RAM (SDRAM) provides valid data is on the RAM after a specific number of clock cycles have elapsed when a read or write command signal is provided to the SDRAM. Several SDRAM design protocols have been developed including DDR DSRAM, Enhanced SDRAM (ESDRAM), PC SDRAM, and DR DRAM (direct RAMBUS DRAM, licensed by RAMBUS Inc.).
Both asynchronous and synchronous RAM protocols also utilize a refresh command to refresh the data stored in selected cells.
As the popularity of SDRAM increases, the use of and availability of EDO RAM in electronic systems decreases. Existing systems utilizing on EDO RAM technologies cannot utilise SDRAM as the asynchronous timing protocols of EDO RAM were not designed to be compatible with SDRAM.
It is desirable to have a system which enables synchronous RAM to be used in systems designed to use EDO RAM or other asynchronous memory device timing protocols.
In a first aspect, the invention provides a method of interfacing an asynchronous memory control system with a synchronous memory device. The method involves receiving a first set of signals indicating an asynchronous memory operation and a first memory address associated with the asynchronous memory operation from the control system. Next, a second set of signals, a second memory address and at least one asynchronous clock pulse are generated. The second set of signals activate a comparable synchronous operation to the asynchronous operation for the synchronous memory device. The comparable synchronous operation is executed on the second memory address. The initiation, duration and frequency of the asynchronous clock pulse(s) comply with requirements of the synchronous memory device to process the synchronous operation.
The method may have the asynchronous clock pulse(s) generated after receiving an edge transition of a signal in the first set of signals. Further, the asynchronous clock pulse(s) may be deasserted after a fixed length of time.
The method may be used where the asynchronous memory control system controls EDO RAM or FAST PAGE RAM.
The method may be used where the synchronous memory is selected from a group comprising SDRAM, PC SDRAM, or synchronous RAM.
The method may process a plurality of read operations for the asynchronous operation with the first set of signals comprising asserting an asynchronous row address strobe signal before asserting a plurality of column address strobe signal followed by deasserting the row address strobe signal. The method may then assert a synchronous activate command before asserting a plurality of synchronous read commands, followed by asserting a synchronous precharge command.
The method may process a plurality of write operations for the asynchronous operation with the first set of signals comprising asserting an asynchronous row address strobe signal followed by asserting a plurality of asynchronous column address strobe signals followed by deasserting the row address strobe signal. The method may then generate the second set of signals comprising asserting a synchronous activate signal then asserting a plurality of synchronous write commands, then asserting a synchronous precharge command.
The method may process a refresh operation for the asynchronous operation with the first set of signals comprising an asserted an asynchronous column address strobe signal before an asserted a row address strobe signal. The method may then generate the second set of signals comprising equivalent refresh signals. Row address strobe and column address strobe signals may be asserted at the same time to generate an equivalent refresh signal.
The method may process an asynchronous operation which is one of a read, a write or a refresh. Further, the method may progress through a plurality of states, wherein each state controls one aspect of generating the second set of signals. Further still, each state may entered according to status of the first set of signals and the each state may be exited with assertion of the asynchronous clock pulse.
In a second aspect, the invention provides a signal converter arrangement for interfacing an asynchronous memory control system with a synchronous memory device. The signal converter arrangement comprises a first set of inputs for receiving from the control system a first set of signals indicating an asynchronous memory operation initiated by the control system and a second set of inputs for receiving a first memory address associated with the asynchronous memory operation. The signal converter has a command generator for receiving the first set of signals, generating a second set of signals of comparable synchronous signals from the first set of signals. The second set of signals activate a comparable synchronous memory operation to the asynchronous memory operation. The command generator also provides the second set of signals to the synchronous memory device. There is also an address generator for generating a second memory address from the first memory address for the synchronous memory operation and providing the second signal set to the synchronous memory device. Further, there is a clock pulse generator for generating at least one asynchronous clock pulse for the synchronous memory operation and providing the asynchronous clock pulse(s) to the synchronous memory device. The signal converter arrangement provides that the second memory address and the asynchronous clock pulse(s) are provided to the synchronous memory device to allow processing of the synchronous operation represented by the second set of signals by the synchronous memory device at the second memory address.
The signal converter arrangement may have the clock pulse generator generating the asynchronous clock pulse(s) after receiving an edge transition of a signal in the first set of signals. Further, the clock pulse generator may deassert the asynchronous clock pulse(s) after a fixed length of time.
The signal converter arrangement may be used where the asynchronous memory control system controls EDO RAM or FAST PAGE RAM.
The signal converter arrangement may be used to control one of a group of synchronous memory protocols comprising SDRAM, PC SDRAM, or SRAM.
The signal converter arrangement may convert a read operation for the asynchronous operation with the first set of signals comprising asserting an asynchronous row address strobe signal before asserting an asynchronous column address strobe signal, followed by deasserting the row address strobe signal. The command generator may generate the second set of signals comprising asserting a synchronous activate command before asserting at least one synchronous read command, followed by asserting a precharge command.
The signal converter arrangement may convert at least one write operation for the asynchronous operation with the first set of signals comprising asserting an asynchronous write enable signal and an asynchronous row address strobe signal followed by asserting at least one asynchronous column address strobe signal before deasserting the row address strobe signal. The command generator may generate the second set of signals comprising asserting a synchronous write enable signal with a synchronous activate command followed by at least one synchronous write command followed by a synchronous refresh command.
The signal converter arrangement may convert a refresh operation for the asynchronous operation with the first set of signals comprising an asserted asynchronous column address strobe signal before an asserted a row address strobe signal. The command generator may generate the second set of signals comprising asserting synchronous refresh command.
The signal converter arrangement may convert the asynchronous operation which is one of a read operation, a write operation or a refresh operation. Further, the signal converter arrangement may have the command generator providing signals based on a plurality of states, wherein each state controls one aspect of generating the second set of signals and progression between two of the plurality of states is controlled by the command generator. Further still, each state may be entered according to status of the first set of signals and the each state may be exited with assertion of the at least one asynchronous clock pulse.